1. Field of the Invention
The present invention relates to a semiconductor device and a method for producing the same. More particularly, the present invention relates to a semiconductor device comprising at least two wiring layers and having a structure in which electric conduction between the two wiring layers can be ensured when a lower wiring layer of the two wiring layers is composed of silicon, and to a method for producing the semiconductor device. In particular, the present invention can be suitably used for a stacked transistor which comprises: a pair of drift layers being formed on a surface layer of a silicon substrate and having a channel therebetween; and a source/drain laminated on the drift layers, and to which a normal scaling law is hard to apply as handling a high voltage or a large electric current.
2. Description of the Related Art
An MOS transistor is known which has a structure in which a conductive region (lower wiring layer) is formed on a surface layer of a silicon substrate by implanting impurities into the substrate, and an upper wiring layer such as a polysilicon layer is directly formed on the conductive region. Since the conductive region is composed of silicon, a natural oxide film grows thereon before the formation of the upper wiring layer. Formation of the upper wiring layer without removing the natural oxide film may result in failure in attaining normal electric conduction between the conductive region and the upper wiring layer. As methods for ensuring the electrical conduction, therefore, there have been proposed a method in which the natural oxide film is removed before the formation of the upper wiring layer, a method in which growth of the natural oxide film is inhibited, and the like. Specifically, the following methods have been proposed.
In Japanese Unexamined Patent Publication No. 2007-5481 (Patent Document 1), a chlorine (Cl2) gas is introduced into a furnace for formation of an upper wiring layer before deposition of the upper wiring layer to remove a natural oxide film on a conductive region.
In Japanese Unexamined Patent Publication No. HEI 9(1997)-213673 (Patent Document 2), Japanese Unexamined Patent Publication No. HEI 7(1995)-153770 (Patent Document 3), and Japanese Unexamined Patent Publication No. HEI 7(1995)-153695 (Patent Document 4), a hydrogen fluoride (HF) gas is introduced into a furnace for formation of an upper wiring layer before deposition of the upper wiring layer to remove a natural oxide film on a conductive region.
In Japanese Unexamined Patent Publication No. SHO 62(1987)-137849 (Patent Document 5), a C3F8 gas is introduced into a reaction chamber of a CVD apparatus for formation of an upper wiring layer and heated before deposition of the upper wiring layer to remove a natural oxide film on a conductive region.
In another method, as disclosed in Japanese Unexamined Patent Publication No. HEI 10(1998)-112488 (Patent Document 6) and Japanese Unexamined Patent Publication No. HEI 8(1996)-306642 (Patent Document 7), a natural oxide film on a conductive region is removed by a reducing gas or plasma treatment in advance in a furnace different from a furnace for deposition of an upper wiring layer before the deposition of the upper wiring layer, and subsequently a silicon substrate is carried to the furnace for the deposition of the upper wiring layer which is filled with an inert gas such as nitrogen, and then the upper wiring layer is formed.
In another method, as disclosed in Japanese Unexamined Patent Publication No. HEI 8(1996)-264453 (Patent Document 8), a silicon substrate is carried to a furnace at a low temperature (150° C. or lower) in order to inhibit oxidation of a surface of a conductive region, and subsequently the inside of the furnace is brought to an inert atmosphere and then heated for deposition of an upper wiring layer, though the concept of the method is different from that of the above-described seven methods.